The present invention relates to a semiconductor device, and particularly to a semiconductor device to which a plurality of circuit blocks are connected via a bus.
In a semiconductor device, there are many suggested bus systems for communicating between a plurality of modules via a bus. In such a bus system, there may be a change in the state of the system such as starting power management control. In this case, the bus system issues a bus stop request to a bus master that issues a transaction to the bus in an attempt to stop issuing new transactions. Then, the bus system waits for the transaction flowing through the bus to complete and changes the state of the system. Examples of the techniques for changing the state of the system including a plurality of modules that are in mutual cooperation are disclosed in Japanese Unexamined Patent Application Publication Nos. 2007-52525 and 2005-122337, and Published Japanese Translation of PCT International Publication for Patent Application, No. 2004-526223.
Japanese Unexamined Patent Application Publication No. 2007-52525 discloses a technique to control supplying and stopping of a signal to a second module by a gate signal generated in response to a request from a first module when memory modules are in the master/slave relationship.
In Japanese Unexamined Patent Application Publication No. 2007-52525, upon a failure in any device among a plurality of devices, usage of the bus by a normally operating bus is restricted except for the case of processing the transactions already issued by the devices. After that, a bus system disclosed in Japanese Unexamined Patent Application Publication No. 2007-52525 outputs bus characteristic information to a bus while resetting the device with the failure on the condition that there is no incomplete transaction and allows the device with the failure to receive the bus characteristic information at the time of cancelling the reset.
Published Japanese Translation of PCT International Publication for Patent Application, No. 2004-526223 discloses a method of broadcasting data to multiple targets across a system bus, such as the peripheral component interconnect (PCI) bus, that does not normally support broadcast transfers, in which one target responds to the bus transaction and the remaining targets listen in on the bus transaction to receive data from the system bus. In Published Japanese Translation of PCT International Publication for Patent Application, No. 2004-526223, the responding target stalls the bus transaction when any of the listening targets communicates to the responding target that they are temporarily unable to accept the data on the bus.